Farrell, Ronan and Ward, Eamon and Brady, Pat (2008) Detection of Coupling Effects in Nanoscale Digital Logic. In: Intel European Research and Innovation Conference , 10-12 September 2008 , Leixlip, Ireland .

Download (19kB)

Abstract

Integrated circuit design is entering an era of truly nanoscale transistors with minimum device geometries now at 32nm and soon to be at 25nm. While actual transistor and logic gate sizes are many times the minimum lengths possible, logic elements are becoming increasingly small and more closely packed together. There is now an increasing possibility of getting coupling errors where nearby logic gates and wires can induce an erroneous response in a logic gate. This has been a significant problem in memory systems for many years where techniques to test for this fault mechanism are well developed. In logic test, there are few methodologies or technologies for detecting this new category of errors.

Item Type:	Conference or Workshop Item (Paper)
Keywords:	Coupling Effects; Nanoscale Digital Logic;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering
Item ID:	1400
Depositing User:	Ronan Farrell
Date Deposited:	26 May 2009 13:13
Refereed:	Yes
URI:
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

Repository Staff Only(login required)

Item control page

Downloads

Origin of downloads