Farrell, Ronan and Ward, Eamon and Brady, Pat
Detection of Coupling Effects in Nanoscale Digital Logic.
In: Intel European Research and Innovation Conference , 10-12 September 2008 , Leixlip, Ireland .
Integrated circuit design is entering an era of truly nanoscale transistors with minimum device geometries now at
32nm and soon to be at 25nm. While actual transistor and logic gate sizes are many times the minimum lengths
possible, logic elements are becoming increasingly small and more closely packed together. There is now an
increasing possibility of getting coupling errors where nearby logic gates and wires can induce an erroneous
response in a logic gate. This has been a significant problem in memory systems for many years where
techniques to test for this fault mechanism are well developed. In logic test, there are few methodologies or
technologies for detecting this new category of errors.
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